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r/FPGA • … • u/Extension_Plate_8927

any feedback on PL sending data to PS DDR by using HP ports.. while petalinux is running ??

Hello,

I’m working with a Zynq UltraScale+ and trying to transfer data from the PL to the PS through an HP port, with the data stored in DDR for the CPU running PetaLinux to process:

FPGA → DDR ← CPU (PetaLinux)

I have a custom AXI4 master that writes data to HP0. this port has some limitations, including a maximum burst length of 16 beats and a 128-bit beat size.

The FPGA can generate data at different rates, but I start losing data when I reach around 2 Gbps. With the same design in bare-metal, I can reach approximately 6-7 Gbps without data loss. PetaLinux itself is running from DDR.

Has anyone implemented a similar design or encountered this issue? I’d appreciate any advice on what might be limiting the transfer rate under PetaLinux.

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