Questions for FPGA teams that heavily utilize "coverage" with verification strategy

I usually equate collecting and analyzing coverage metrics with ASIC oriented development. My knowledge of coverage goes towards "functional coverage" where you're coding actual cover points in RTL and tweak your tests to see if you can hit them vs. "code coverage" which is a less stringent form of coverage to see how many lines of code get exercised.

Was wondering how many FPGA teams actually heavily use coverage in their verification strategy? If so, what tools do you use? Are you coding cover points in actual RTL? Are you utilizing some form of co-sim environment where can run faster than a pure simulation (UVM, system verilog) environment?